JPH0131687B2 - - Google Patents

Info

Publication number
JPH0131687B2
JPH0131687B2 JP56125460A JP12546081A JPH0131687B2 JP H0131687 B2 JPH0131687 B2 JP H0131687B2 JP 56125460 A JP56125460 A JP 56125460A JP 12546081 A JP12546081 A JP 12546081A JP H0131687 B2 JPH0131687 B2 JP H0131687B2
Authority
JP
Japan
Prior art keywords
lead
lead pins
semiconductor chip
frame
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56125460A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5827332A (ja
Inventor
Yoshio Shimizu
Shigeki Takeo
Iwao Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP12546081A priority Critical patent/JPS5827332A/ja
Publication of JPS5827332A publication Critical patent/JPS5827332A/ja
Publication of JPH0131687B2 publication Critical patent/JPH0131687B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
JP12546081A 1981-08-11 1981-08-11 リードフレームを用いた半導体装置の製造方法 Granted JPS5827332A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12546081A JPS5827332A (ja) 1981-08-11 1981-08-11 リードフレームを用いた半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12546081A JPS5827332A (ja) 1981-08-11 1981-08-11 リードフレームを用いた半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5827332A JPS5827332A (ja) 1983-02-18
JPH0131687B2 true JPH0131687B2 (en]) 1989-06-27

Family

ID=14910636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12546081A Granted JPS5827332A (ja) 1981-08-11 1981-08-11 リードフレームを用いた半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5827332A (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2519806B2 (ja) * 1989-09-12 1996-07-31 株式会社東芝 樹脂封止型半導体装置
US5343072A (en) * 1990-08-20 1994-08-30 Rohm Co., Ltd. Method and leadframe for making electronic components

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559749A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Lead frame

Also Published As

Publication number Publication date
JPS5827332A (ja) 1983-02-18

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